Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are fabricated on a surface of a wafer, or alternatively, on a surface of a previous layer. This fabrication process typically requires subsequent layers to be fabricated upon a smooth, planar surface of a previous layer. However, the surface topography of layers may be uneven due to an uneven topography associated with an underlying layer. As a result, a layer may need to be polished in order to present a smooth, planar surface for a subsequent processing step. For example, a layer may need to be polished prior to formation of a conductor layer or pattern on an outer surface of the layer.
In general, a semiconductor wafer may be polished to remove high topography and surface defects such as scratches, roughness, or embedded particles of dirt or dust. The polishing process typically is accomplished with a polishing system that includes top and bottom platens (e.g. a polishing table and a wafer carrier or holder), between which the semiconductor wafer is positioned. The platens are moved relative to each other thereby causing material to be removed from the surface of the wafer. This polishing process is often referred to as mechanical planarization (MP) and is utilized to improve the quality and reliability of semiconductor devices. The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates, along with the selective removal of materials fabricated on the semiconductor wafer. This polishing process is often referred to as chemical mechanical planarization or chemical mechanical polishing (CMP).
Such polishing processes typically removes the topographic features of a number of alignment marks associated with the semiconductor wafer. Alignment marks are features such as a number of horizontal and vertical trenches defined in the semiconductor wafer at predetermined locations throughout the wafer which are utilized by fabrication equipment during various steps of wafer fabrication. For example, photolithographic steppers, which pattern images onto the wafer during fabrication thereof, utilize the alignment marks for aligning the semiconductor wafer with a corresponding patterning tool. In particular, prior to imaging a pattern on the semiconductor wafer, the photolithographic stepper aligns a patterning tool associated therewith to the alignment marks by detecting the edges of the alignment marks. It should therefore be appreciated that the alignment marks must be exposed or otherwise clearly defined prior to imaging of a pattern onto the semiconductor wafer.
Traditionally, subsequent to polishing of the semiconductor wafer, the alignment marks are "cleared" or "exposed" by performing a print and etch process in which a layer of resist is initially patterned on the wafer. Thereafter, the wafer is etched by use of an etcher such as a plasma etcher such that material (e.g. residual metal, dielectric, or other debris) in the trenches of the alignment mark is removed from the wafer in the area proximate the alignment mark thereby exposing or otherwise clearing the alignment mark for subsequent use thereof.
A plasma etcher typically consists of a vacuum chamber having a reactant gas present therein. A semiconductor wafer is positioned on an alignment mechanism so as to be positioned or aligned in a predetermined orientation. Thereafter, the semiconductor wafer is positioned within the vacuum chamber by a robotic arm mechanism. Application of an electric field within the vacuum chamber (e.g. an electric field at either RF or microwave frequencies) causes the reactant gas to be broken down thereby generating a plasma. Reactant species present in the plasma etch or otherwise remove the wafer material that is intended to be removed (i.e. material not covered or otherwise layered with a resist layer). Hence, in regard to fabrication methods which have heretofore been utilized to clear alignment marks, a resist layer is initially patterned on the wafer such that the areas proximate the alignment marks are exposed or otherwise not covered by the resist layer. Thereafter, the wafer is etched in the plasma etcher such that the material disposed on the alignment mark is etched by the plasma present in the vacuum chamber.
However, the above-described prior art method of clearing alignment marks has a number of drawbacks associated therewith. For example, the above-described prior art method of clearing alignment marks undesirably requires a printing step for printing a masking layer onto the wafer prior to the etching step associated with clearing the alignment marks. Such an additional step undesirably increases costs associated with manufacture of the semiconductor wafer.
Thus, a continuing need exists for a method and an apparatus which accurately and efficiently removes residual material or debris from an alignment mark subsequent to polishing of a semiconductor wafer. What is specifically needed is a method and an apparatus which accurately and efficiently removes material from an alignment mark subsequent to polishing of a semiconductor wafer which reduces the number of fabrication steps relative to prior art methods and apparatuses for removing material from an alignment mark.